The present invention relates to a control system of first-in-first-out (hereafter abbreviated as FIFO) memories, and more particularly to a control system of FIFO memories used for recording/reproducing audio signals.
The FIFO memories have been used in audio interface units for recording/reproducing audio signals without interruption, whereof examples are disclosed in a Japanese utility model registration application laid open as a Provisional Publication No. 180338/'86 and a Japanese patent application laid open as a Provisional Publication No. 232246/'87.
FIG. 6 is a block diagram illustrating an example of the conventional FIFO memory control systems applied to a sound codec device. Referring to FIG. 6, audio signals are input from a microphone 101 to an A/D (Analog to Digital) converter 102. Output of the A/D converter 102 is input to an input FIFO memory 103. A CPU 104 receives data from the input FIFO memory 103. The CPU 104 delivers data to an output FIFO memory 107, output thereof being input to a D/A (Digital to Analog) converter 106. Output of the D/A converter 106 is supplied to a speaker 105 to reproduce audio output.
The FIFO memories are used as follows.
In recording operation, a sound signal output of the microphone 101 is converted into digital data through the A/D converter 102, which are stored in the input FIFO memory 103. Then, at a timing when the input FIFO memory 103 is filled with the digital data, they are read out by the CPU 104 at once. The sampling frequency of the A/D converter, which converts the sound signal from the microphone 101, is about several ten KHz, while the transfer bit rate of the CPU 104 is, generally, about several ten MHz. Therefore, all the digital data stored in the input FIFO memory can be transferred to the CPU 104 within one sampling interval of the sound signal without missing any sampling, on condition the input FIFO memory 103 is not too large.
In reproduction operation, an amount of digital data to be reproduced for filling the output FIFO memory 107 are transferred at once from the CPU, which are read out successively to be converted into analog signals by the D/A converter 106 to be reproduced. At each timing when all the digital data in the output FIFO memory 107 are read out, the same amount of the digital data are transferred from the CPU 104 repeatedly until all the reproduction data are transferred. Here, also in the reproduction, the digital data in the output FIFO memory 107 can be reproduced without interruption, since each data transfer, at the transfer bit rate of several ten MHz, is performed within an interval for reading out successive sampled data.
However, usage of each of the FIFO memories is fixed for each of sound recording and sound reproduction, in the conventional FIFO memory control systems. Therefore, the input FIFO memory 103 is left unused when the sound codec is used only for sound reproduction, while the output FIFO memory 107 is left unused when the sound codec is used only for sound recording. This is a problem.